As a semiconductor device having trenches, a trench capacitor memory cell of a DRAM is well known.
Improvement in the integration degree of a memory device such as the DRAM has been advanced year by year. Thus, process development has not been able to keep up with reduction in a memory cell size. It has emerged that, if trenches, for example, deep trenches (DTs) are used to form capacitors of DRAM memory cells, there is a close relationship between a layout of the DTs and a process margin.